Talk: Energy Efficient Platforms for High Performance and Embedded Computing, 1pm 12/7

UMBC CSEE Colloquium

Energy Efficient Platforms for
High Performance and Embedded Computing

Dr. Tinoosh Mohsenin
Computer Science and Electrical Engineering
University of Maryland, Baltimore County

1:00pm Friday, 7 December 2012, ITE 227, UMBC

Future embedded, high performance, and cloud computing must meet limited energy capacity, cost, and sustainability. These devices will regularly execute over one tera-operations per second (TOPS) with a variety of diverse workloads—from baseband communications to wearable medical devices—while operating on a 5 to 25 Watt-hour cellphone/tablet battery. The need for greater energy efficiency, smaller size and improved performance of these devices demands a co-optimization of algorithms, architectures, and implementations. This talk presents several programmable and application specific solutions that illustrate the cross-domain optimization.

The design of system-on-Chip blocks becomes increasingly sophisticated with emerging real-time computational and limited power budget requirements. Two such algorithms, Low Density Parity Check (LDPC) decoding and Compressive Sensing (CS), have received significant attention. LDPC decoding is an error correction technique which has shown superior error correction performance and has been adopted by several recent communication standards. Compressive sensing is a revolutionary technique which significantly reduces the amount of data collected during acquisition. While both LDPC decoding and compressive sampling have several advantages, they require high computational intensive algorithms which typically suffer from high power consumption and low clock rates. We present novel algorithms and architectures to address these challenges.

As future systems demand increasing flexibility and performance within a limited power budget, many-core chip architectures have become a promising solution. The design and implementation of a programmable many-core platform containing 64 cores routed in a hierarchical network is presented. For demonstration, Electroencephalogram (EEG) seizure detection and analysis and ultrasound spectral doppler are mapped onto the cores. The seizure detection and analysis takes 900 ns and consumes 240 nJ of energy. Spectral doppler takes 715 ns and consumes 182 nJ of energy. The prototype is implemented in 65 nm CMOS which contains 64 cores, occupies 19.51 mm2 and runs at 1.18 GHz at 1 V.

Dr. Tinoosh Mohsenin is an assistant professor in the Department of Computer Science and Electrical Engineering at the University of Maryland Baltimore County since 2011. Prior to joining UMBC, she was finishing her PhD at the University of California, Davis. Dr. Mohsenin’s research interests lie in the areas of high performance and energy-efficiency in programmable and special purpose processors. She is the director of Energy Efficient High Performance Computing (EEHPC) Lab where she leads projects in architecture, hardware, software tools, and applications for VLSI computation with an emphasis on digital signal processing workloads. She has been consultant to early stage technology companies and currently serves in the Technical Program Committees of the IEEE Biomedical Circuits & Systems Conference (BioCAS), Life Science Systems and Applications Workshop (LiSSA), International Symposium on Quality Electronic Design (ISQED) and IEEE Women in Circuits and Systems (WiCAS).

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